In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals produced by a semiconductor test system at its appropriate pins at predetermined test timings. The test system receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed, i.e., sampled, by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly.
Timings of the test signals and strobe signals are defined, for example, relative to a tester rate or a tester cycle of the semiconductor test system. In a such a semiconductor test system, the semiconductor device under test (DUT) is tested by providing a cycled pin pattern vectors at a programmed data rate (tester cycle) to a formatter with timing edges to produce the desired waveforms of the test signals and the strobe signals.
Generally, the various timings of the tester cycles, test signals and strobe signals are generated based on a clock signal such as a reference clock or system clock. The reference clock is produced by a high stability oscillator, for example, a crystal oscillator provided in the IC tester. When the required timing resolution in an test system is equal to or an integer multiple of the highest clock rate (shortest clock cycle) of the reference clock oscillator, variety of timing signals can be generated by simply dividing the reference clock by a counter or a divider.
However, semiconductor test systems are usually required to have timing resolution higher than the highest clock rate, i.e., the shortest time period, of the reference (system) clock. For example, in the case where a reference clock used in an IC tester is 10 ns (nanosecond), but the IC tester needs to have timing resolution of 0.3 ns or higher, it is not possible to achieve such timing resolution by simply applying or dividing the reference clock. Thus, a timing generator for generating high resolution timing signals includes a fine variable delay circuit which is able to produce a delay time smaller than a time length of one clock cycle in response to timing data provided thereto.
Moreover, in order to generate timing signals of high frequency repetition rate without using very high speed circuit components, a timing generator may have an interleave architecture. In an interleave based timing generator, a plurality of timing generation circuits are incorporated in a parallel fashion. The output signals of such timing generation circuits are combined to produce signals in a series fashion so that the resultant timing signals have a high repetition rate even though a timing signal in each of the parallel circuits has a relatively low frequency.
The conventional semiconductor test system having such an interleave based timing generator having fine variable delay circuits is described with reference to FIGS. 5-7. FIG. 5a is a schematic diagram showing a basic structure of the conventional semiconductor test system and FIG. 5b shows waveforms for producing a test signal to be supplied to a device under test (DUT).
In the example of FIG. 5a, the semiconductor test system includes a pattern generator 12, a set pulse generator 14 having a timing data generator TGD.sub.S and a variable delay circuit 29, a reset pulse generator 15 having a timing data generator TGD.sub.R and a variable delay circuit 39, a flip-flop 70 which is typically a set-reset flip-flop, and a driver 18. Based on the foregoing arrangement, the output of the driver 18 provides a test signal to a terminal pin of a device under test (DUT) 20.
As is known in the art, a high end semiconductor test system has a per-pin architecture in which test signals of desired timings can be generated by each tester pin (test channel) independently from the other tester pins. In other words, each of the tester pins includes the pattern generator 12, the set pulse generator 14, the reset pulse generator 15, the flip-flop 70 and the driver 18. The number of tester pins must be sufficient to the number of terminal pins of anticipated devices to be tested, which may be as many as several hundreds to one thousand. For the simplicity of explanation, in the present invention, only one of such tester pins is described although there are many tester pins in the actual test system.
In the example of FIG. 5a, the pattern generator 12 generates test pattern signals with a wave shaped manner which is provided to the set pulse generator 14 and the reset pulse generator 15. The pattern generator 12 also provides timing information to the set pulse generator 14 and the reset pulse generator 15 as will be described with reference to FIG. 6. The set pulse generator 14 and the reset pulse generator 15 have identical structure to one another. As shown in FIG. 5b, when receiving the test pattern signal from the pattern generator 12, the set pulse generator 14 outputs a set pulse signal SP10 having a predetermined delay timing. Similarly, the reset pulse generator 15 outputs a reset pulse signal RP11 having a predetermined delay timing. Upon receiving both the set pulse and reset pulse mentioned above, the flip-flop 70 generates a test wave W1 to be applied to the DUT 20 via the driver 18.
The more specific configuration of the set pulse generator 14 is explained with reference to FIG. 6. As noted above, the reset pulse generator 15 has substantially the same configuration as that of the set pulse generator 14. Here, the number of phase L in the interleave architecture is four, i.e., four timing signals are processed in parallel and combined together to form a series timing signal. Depending on the test speed desired, the interleave architecture may be configured to have different number of phases such as two phases, eight phases or more.
In the example of FIG. 6, since the number of phase L=4 and high speed test signals having a frequency of four times higher than the signals processed in each of the parallel circuit can be generated. For example, when the maximum test frequency (test rate) is 500 MHz, the frequency of 125 MHz, that is one-fourth of the maximum frequency, can be handled by the parallel circuits. Thus, low frequency circuits can generate a high frequency signal although the number of circuit components must be increased.
In FIG. 6, the set pulse generator 14 includes timing pulse generators (1)-(4). The outputs of the timing pulse generators (1)-(4) are connected to an OR circuit 27 wherein they are combined to produce a series signal (set pulse SP10) which is supplied to the set terminal of the flip-flop 70. Each of the timing pulse generators (1)-(4) includes a timing data generator TGD, a pulser 28 and a variable delay circuit 29. The pattern generator PG1-PG4 produces, among others, timing information based on a test program to produce test waves to be supplied to the device under test. The pattern generators PG1-PG4 may also have an interleave structure so that each pattern generator PG provides the set pulse timing information to the corresponding timing data generator TGD in response to a test clock T.sub.clk1.
In the timing pulse generator (1), upon receiving the set pulse timing information from the pattern generator PG1, the timing data generator TGD1 generates a coarse set signal G1 which may be delayed from the previous set signal by an integer multiple of the test clock T.sub.clk1. The repetition rate of the coarse set signal G1 defines a tester rate of the current test cycle in the test system. The timing data generator TGD also generates high resolution delay data HR1 having an M-bit width. The size of the M-bit width differs depending on the delay accuracy of the test system, and is configured by, for example, 10 bits.
Upon receiving the coarse set signal G1 from the timing data generator TGD1, the pulser 28 outputs a pulse signal P1 in synchronism with the signal G1 having a predetermined pulse width. The pulse signal P1 is provided to the variable delay circuit 29.sub.1 wherein a high resolution delay time smaller than the test clock cycle is added.
As shown in FIG. 7a, a basic form of the variable delay circuit 29 is an analog type fine variable delay circuit 38. The maximum delay time of which is, for example, one cycle length of the test clock T.sub.clk1 such as eight 8 nS (nanosecond). Typically, such a variable delay circuit is formed of a large number of series connected semiconductor components, such as CMOS gates whose signal propagation delay times are regulated by changing the voltages supplied thereto. Such a variable delay circuit is well known in the art and is frequently used in a semiconductor test system for producing timing signals of high resolution.
Upon receiving the high resolution delay data HR1 from the timing data generator TGD1, the variable delay circuit 29.sub.1 adds a high resolution delay time defined by the data HR1 to the pulse signal P1. The timing resolution of the variable delay circuit 29.sub.1 is, for example, in the order of several ten picoseconds. Thus, a set pulse signal SP1 having a high resolution delay time is produced by the variable delay circuit 29.sub.1 and is provided to the input of the OR circuit 27. This set pulse signal SP1 defines a rising edge of the test signal W1 to the DUT 20.
In the similar manner, the timing pulse generators (2), (3) and (4) respectively provide set pulse signals SP2, SP3 and SP4 to the OR circuit 27. Thus, the OR gate 27 receives four pulse signals in parallel and outputs the set pulse signal SP10 that is a logical sum of the four pulse signals. In other words, the set pulse generator 14 functions as a parallel to serial converter.
The flip-flop 70 is a set/reset type flip-flop, such as an RS flip-flop. The flip-flop 70 receives the set pulse signal SP10 from the set pulse generator 14 at the set terminal, thereby setting the output to a high level. Similarly, the flip-flop 70 receives the reset pulse signal RP11 from the reset pulse generator 15 at the reset terminal, thereby setting the output to a low level. Accordingly, the flip-flop 70 generates the test wave W1 having a rising edge defined by the set pulse signal and a falling edge defined by the reset pulse signal. The test wave W1 is supplied to the DUT 20 through the driver 18.
In the conventional technology, the timing generator described above has a drawback in terms of timing accuracy when generating the test wave W1. The timing accuracy problem arises in the parallel structure of the variable delay circuits 29.sub.1 -29.sub.4. As in the foregoing, the variable delay circuit 29 is provided in each of the four phases of the interleave configuration and is alternately selected to produce a series signal. Thus, the variable delay circuit 29 generates the set pulse signal SP1-SP4 (or reset pulse RP1-RP4) with the predetermined timings.
As noted above, variable delay circuits 29 are typically configured by series connected delay elements, typically CMOS gates, whose delay times are usually different from one another. Further, the delay times of the CMOS gates show different characteristics in response to the changes of the ambient temperature. Because such differences in the delay elements, each variable delay circuit 29 for each phase is not exactly identical to the other. As a result, each of the set pulse signals SP1-SP4 from the variable delay circuit is fluctuated differently from the other.
As a consequence, for the timing relationship A of FIG. 7b, the set pulse signals as shown by a reference label B of FIG. 7b are resulted which has relative timing fluctuations, i.e., interleave (phase) jitters. Typically, the maximum jitter in such a situation is equivalent to two times of the maximum timing resolution. Therefore, if the maximum timing resolution of the intended timing generator is 50 picoseconds, the maximum jitter of 100 picoseconds can be attached to the set pulse signals. The similar jitters are produced in the reset pulse signals as well in the similar manner. In addition, because the variable delay circuits have different temperature characteristics as noted above, the relative delay times among the set pulses and among the resent pulses will be fluctuated when interleaved according to the change of the temperature.
Thus, the conventional timing generator is undesirable because interleave jitters and relative timing fluctuations are involved in the test wave to be applied to the DUT. Since the timing accuracy in the semiconductor test system is one of the most important factors, the interleave jitters and relative timing fluctuations are serious drawbacks in the semiconductor testing. Moreover, provision of the variable delay circuit at each phase of the interleave architecture increases the size and circuit components of the semiconductor test system.